1. Field of the Invention
This invention relates to integrated circuit structures and processes for making integrated circuit structures and more particularly to processes for making static random access memory having fewer pipeline defects.
2. Description of Related Art
Integrated circuits having small feature size are sensitive to defects. For example, pipeline defects, which are conductive crystalline defects that underlie the gates of transistors and cause source-drain shorts, are more common in CMOS field effect transistors having short channel length. As described by H. Belgal et al., in "A New Mechanism of Pipeline Defect Formation in CMOS Devices", 1994 Proceedings of IEEE/IRPS, pp. 399-404; and by C. T. Wang et al., in "Pipeline Defects in CMOS Devices Caused by SWAMI Isolation" 1992 Proceedings of IEEE/IRPS, pp. 85-90, stresses from field oxidation and/or ion implantation near a transistor may cause crystalline defects under the transistor's gate. Dopants, metal, or hydrogen can enter and activate such crystalline defects to create a conductive path or short between the source and drain of the transistor.
Pipeline defects are a problem in memory cells such as the 4-transistor static random access memory (SRAM) cell 100 shown in FIG. 1. SRAM cell 100 contains a pair of N-channel pull-down transistors Q1 and Q2, a pair of pull-up resistors R1 and R2, and a pair of N-channel pass transistors Q3 and Q4. Pull-down transistors Q1 and Q2 connect respective nodes 110 and 120 to a reference voltage Vss (ground) and are cross-coupled so that the gate of transistor Q1 couples to the drain of transistor Q2 (node 120) and the gate of transistor Q2 couples to the drain of transistor Q1 (node 110). Pull-up resistors R1 and R2 connect respective nodes 110 and 120 to a supply voltage Vcc. In operation, memory cell 100 has two stable states distinguished by pull-down transistor Q1 or pull-down transistor Q2 being turned on. In both stable states, the voltage on node 110 is complementary to the voltage on node 120, i.e. the voltage on node 110 is high (near supply voltage Vcc) when the voltage on node 120 is low (near reference voltage Vss) and is low when the voltage on node 120 is high.
Pass transistors Q3 and Q4 are coupled between respective nodes 110 and 120 and respective bit lines 115 and 125 and have gates coupled to a word line 130. If SRAM cell 100 is selected, the voltage on word line 130 turns on pass transistors Q3 and Q4 and connects nodes 110 and 120 to respective bit lines 115 and 125. Voltages on nodes 110 and 120 change currents or voltages on bit lines 115 and 125 which are sensed during reading of SRAM cell 100. If SRAM cell 100 is not selected, the voltage on word line 130 is low to turn off pass transistors Q3 and Q4. However, if pass transistor Q3 or Q4 has a pipeline defect, the defective pass transistor Q3 or Q4 conducts and changes the voltages and currents on bit lines 115 and 125 even when SRAM cell 100 is not selected. Accordingly, pipeline defects in unselected cells can cause read errors.
Integrated circuit structures and processes are sought which reduce occurrences of pipeline defects.